A 5-Gb/s counter-based adaptive equalizer in 180-nm CMOS
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https://doi.org/10.54939/1859-1043.j.mst.78.2022.58-67Keywords:
Adaptive Equalizer (EQ); Continuous-time linear EQ; Counter-based EQ; CMOS EQ; High-speed serial communication.Abstract
This paper presents a counter-based adaptive equalizer without using analog circuits to minimize the influence of process, temperature, and power supply variation on equalization performance. A counter-based adaptive loop is proposed for the equalizer to achieve a short adaptation time and low power consumption. The edges of the sampled data are counted to compensate for the loss of the high-speed serial channel. The adaptive equalizer is designed on 180-nm CMOS technology. In the simulation, the equalizer has a compensation range of 27.8-dB at a data rate of 5-Gb/s, obtains an adaptation time of 4.42-us, and power consumption of 14.04-mW from a single 1.8-V supply.
References
[1]. Lee, Jri (2006), "A 20-Gb/s Adaptive Equalizer in 0.13-µm CMOS Technology", IEEE Journal of Solid-State Circuits. 41(9), pp. 2058-2066.
[2]. Cheng, Kuo-Hsing, et al. (2010), "A 5-Gb/s inductorless CMOS adaptive equalizer for PCI express generation II applications", IEEE Transactions on Circuits and Systems II: Express Briefs. 57(5), pp. 324-328.
[3]. Kim, Yong-Hun, et al. (2015), "A 21-Gbit/s 1.63-pJ/bit adaptive CTLE and one-tap DFE with single loop spectrum balancing method", IEEE Transactions on Very Large Scale Integration (VLSI) Systems. 24(2), pp. 789-793.
[4]. Nakhkoob, Behrooz and Hella, Mona Mostafa (2016), "A 4.7-Gb/s Reconfigurable CMOS Imaging Optical Receiver Utilizing Adaptive Spectrum Balancing Equalizer", IEEE Transactions on Circuits and Systems I: Regular Papers. 64(1), pp. 182-194.
[5]. Lee, Dongmyung, et al. (2010), "An 8.5-Gb/s fully integrated CMOS optoelectronic receiver using slope-detection adaptive equalizer", IEEE Journal of Solid-State Circuits. 45(12), pp. 2861-2873.
[6]. Seong, Chang-Kyung, Rhim, Jinsoo, and Choi, Woo-Young (2012), "A 10-Gb/s adaptive look-ahead decision feedback equalizer with an eye-opening monitor", IEEE Transactions on Circuits and Systems II: Express Briefs. 59(4), pp. 209-213.
[7]. Son, Seuk, et al. (2013), "A 2.3-mW, 5-Gb/s low-power decision-feedback equalizer receiver front-end and its two-step, minimum bit-error-rate adaptation algorithm", IEEE Journal of Solid-State Circuits. 48(11), pp. 2693-2704.
[8]. Won, Hyosup, et al. (2016), "A 28-Gb/s receiver with self-contained adaptive equalization and sampling point control using stochastic sigma-tracking eye-opening monitor", IEEE Transactions on Circuits and Systems I: Regular Papers. 64(3), pp. 664-674.
[9]. Kim, Wang Soo, Seong, Chang Kyung, and Choi, Woo Young (2011), “A 5.4 Gb/s adaptive equalizer using asynchronous-sampling histograms”, 2011 IEEE International Solid-State Circuits Conference, ISSCC 2011, pp. 358-359.
[10]. Lin, Yuan-Fu, et al. (2014), “A 5–20 Gb/s power scalable adaptive linear equalizer using edge counting”, 2014 IEEE Asian Solid-State Circuits Conference (A-SSCC), IEEE, pp. 273-276.
[11]. Choi, Yoonjae, et al. (2021), "A 0.99-pJ/b 15-Gb/s Counter-Based Adaptive Equalizer Using Single Comparator in 28-nm CMOS".
[12]. B. Razavi, “TSPC Logic,” IEEE Solid-State Circuits Magazine, 2016.
[13]. M. Green, “Shunt-Peaking,” EECE 270C, Winter 2013.
[14]. N. H. Thọ, et al., “Thiết kế mạch khôi phục dữ liệu và xung đồng hồ dải rộng, không sử dụng tần số tham chiếu, tốc độ dữ liệu liên tục sử dụng công nghệ CMOS 180 nm,” Tạp chí Nghiên cứu khoa học và công nghệ quân sự, Số 63, 2019.
