A 5-Gb/s counter-based adaptive equalizer in 180-nm CMOS
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https://doi.org/10.54939/1859-1043.j.mst.78.2022.58-67Keywords:
Adaptive Equalizer (EQ); Continuous-time linear EQ; Counter-based EQ; CMOS EQ; High-speed serial communication.Abstract
This paper presents a counter-based adaptive equalizer without using analog circuits to minimize the influence of process, temperature, and power supply variation on equalization performance. A counter-based adaptive loop is proposed for the equalizer to achieve a short adaptation time and low power consumption. The edges of the sampled data are counted to compensate for the loss of the high-speed serial channel. The adaptive equalizer is designed on 180-nm CMOS technology. In the simulation, the equalizer has a compensation range of 27.8-dB at a data rate of 5-Gb/s, obtains an adaptation time of 4.42-us, and power consumption of 14.04-mW from a single 1.8-V supply.
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