AN FPGA-BASED HARDWARE ACCELERATOR DATA SYNCHRONIZATION FROM DIGITAL RECEIVERS

Authors

  • Dinh Van Ngoc Academy of Military Science and Technology

Keywords:

FPGA; FPGA-based Accelerator; Parallel processing; Pipelined architecture.

Abstract

At present, the integrated density on digital integrated circuits has reached billions of transistors on a single chip, allowing the creation of dedicated hardware devices to accelerate the data processing, analysis, and searching of the large stream-based input data. The problem of processing big data obtained from digital receivers often encounters noise interference and phase deviation, leading to the need to analyze and rearrange them in the correct order for the next processing stages. If performed on software, these works are often inefficient because the processing speed does not meet the requirements. This paper proposes a searching and processing accelerator design for large stream-based data obtained from digital receivers, using a combination of parallel processing algorithms and pipeline techniques; conducts evaluations of the factors affecting the searching speed, and utilized resources to come up with the optimal design solution. We implemented the design on the Kintex 7-XC7K325T FPGA board for parallel data searching with a pattern length of 128 bits, using up to 512 comparison blocks at 100 MHz clock frequency and different modulation types such as PSK and QAM. Hardware performance is about 945 times faster than on the software with a maximum bandwidth of 800 Mbps.

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Published

2021-02-25

How to Cite

[1]
N. Đinh Văn, “AN FPGA-BASED HARDWARE ACCELERATOR DATA SYNCHRONIZATION FROM DIGITAL RECEIVERS”, JMST, no. 71, pp. 88-97, Feb. 2021.

Issue

Section

Articles