Design and evaluation of sphere decoder accelerator on reconfiguration hardware

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Authors

  • Nguyen Minh Thuong Academy of Military Science and Technology
  • Tran Xuan Nam Military Technical Academy
  • Nguyen Duc Thang Military Technical Academy
  • Vu Tien Anh Military Technical Academy
  • Trinh Quang Kien (Corresponding Author) Military Technical Academy

DOI:

https://doi.org/10.54939/1859-1043.j.mst.80.2022.80-91

Keywords:

MIMO; FPGA; SM; SD; ML.

Abstract

 The Maximum likelihood (ML) detection can achieve the best bit error rate but requires very high computational complexity. The latter makes this algorithm is not practically applicable. Many decoder architectures hence have been proposed to overcome the ML high complexity. The sphere decoding (SD) algorithm is one of the most promising approaches that offer quasi-ML performance with a reasonable computing workload. This paper proposes an efficient and practical approach for a sphere decoder design on reconfigurable hardware (FPGA). The design is evaluated to yield a quality approximation of the Maximum Likelihood (ML) method but with significantly reduced computational complexity.

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Published

28-06-2022

How to Cite

Nguyễn Minh Thường, Trần Xuân Nam, Nguyễn Đức Thắng, Vũ Tiến Anh, and Trịnh Quang Kiên. “Design and Evaluation of Sphere Decoder Accelerator on Reconfiguration Hardware”. Journal of Military Science and Technology, no. 80, June 2022, pp. 80-91, doi:10.54939/1859-1043.j.mst.80.2022.80-91.

Issue

Section

Research Articles