Designing and simulation a 15-bit successive approximation register analog-to-digital converter

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Authors

  • Pham Duy Phong Faculty of Electronics and Telecommunication Engineering, Electric Power University;
  • Pham Xuan Thanh Faculty of Electronics Engineering, Ha Noi University of Industry
  • Nguyen Thi Viet Ha Faculty of Electronics Engineering, Ha Noi University of Industry
  • Hoang Manh Kha (Corresponding Author) Faculty of Electronics Engineering, Ha Noi University of Industry

DOI:

https://doi.org/10.54939/1859-1043.j.mst.87.2023.1-8

Keywords:

Analog-to-digital converters; Successive approximation register; Binary weighted with attenuation capacitor.

Abstract

Analog-to-digital converters (ADC) are widely employed to monitor long-term signal characteristics in wireless sensor networks and healthcare electronic devices. It is critical in these applications to use an energy-efficient ADC to extend battery life. This paper presents a 15-bit successive-approximation register (SAR) ADC for using in biomedical processing systems. The segmentation degrees (the amount of bits in each divided capacitive sub-array) are optimized to minimize switching power and area based on linearity and matching requirements. The proposed SAR ADC is simulated by using Simulink of Matlab. The simulated results show that the ADC achieves 14.78-bit of effective numbers of bits (ENoB), 111.5 dB of the spurious-free dynamic range (SFDR) with 90.74 dB of signal-to-noise ratio (SNR) at a sampling rate of 10MHz.

References

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Published

25-05-2023

How to Cite

Pham, D. P., T. Pham Xuan, Nguyen Thi Viet Ha, and M. K. Hoang. “Designing and Simulation a 15-Bit Successive Approximation Register Analog-to-Digital Converter”. Journal of Military Science and Technology, vol. 87, no. 87, May 2023, pp. 1-8, doi:10.54939/1859-1043.j.mst.87.2023.1-8.

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