TPC decoder design for FPGA implementation

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Authors

  • Nguyen Van Phe (Corresponding Author) Trung tâm Kỹ thuật Thông tin Công nghệ cao
  • Dang Van Binh Trung tâm Kỹ thuật Thông tin Công nghệ cao
  • Nguyen Thien Tan University of Economics - Technology for Industries
  • Le Van Hong Trung tâm Kỹ thuật Thông tin Công nghệ cao

DOI:

https://doi.org/10.54939/1859-1043.j.mst.85.2023.26-34

Keywords:

TPC; SISO; Chase-Pyndiah algorithm; QAM; FPGA.

Abstract

In this paper, the FPGA implementation of Turbo Product Code is presented. The design is based on the iterative decoding structure with using Chase-Pydiah algorithm for better decoding performance. In pacticular, circuit design and implementation based on the simplified algorithm without using multiplication. Simulation and implementation result show that, the decoding perfomance of this presented algorithm is not reduced. The 800Mbps TPC deccoder was achieved for FPGA implementation on the Xilinx Artix7 xc7a200tfbg484-1 platform at the 200MHz system clock.

References

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Published

28-02-2023

How to Cite

Nguyễn Văn, P., B. Đặng Văn, Nguyễn Thiên Tân, and H. Lê Văn. “TPC Decoder Design for FPGA Implementation”. Journal of Military Science and Technology, vol. 85, Feb. 2023, pp. 26-34, doi:10.54939/1859-1043.j.mst.85.2023.26-34.

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